I/O Buffer Placement Methodology for ASICs

In modern designs, voltage drop on the power grid is becoming a critical concern. One important technique to avoid severe voltage drops is to spread the highly power hungry buffers, such as I/O buffers, around the grid. In this paper, we study the problem of I/O buffer placement so as to avoid hot spots which are locations on the chip characterized by high voltage drops. The problem is defined mathematically and formulated as an ILP problem. Then an efficient greedy heuristic is proposed as an alternative to the expensive ILP solution.